Function report | 
Source Code:arch\x86\kernel\apic\apic.c | 
Create Date:2022-07-28 08:26:37 | 
| Last Modify:2020-03-16 21:21:31 | Copyright©Brick | 
| home page | Tree | 
| Annotation kernel can get tool activity | Download SCCT | Chinese | 
Name:This function sets up the local APIC timer, with a timeout of* 'clocks' APIC bus clock. During calibration we actually call* this function twice on the boot CPU, once with a bogus timeout* value, second time for real. The other (noncalibrating) CPUs
Proto:static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
Type:void
Parameter:
| Type | Parameter | Name | 
|---|---|---|
| unsigned int | clocks | |
| int | oneshot | |
| int | irqen | 
| 334 | lvtt_value = LOCAL_TIMER_VECTOR | 
| 335 | If Not oneshot Then lvtt_value |= APIC_LVT_TIMER_PERIODIC | 
| 337 | Else if boot_cpu_has(TSC deadline timer ) Then lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE | 
| 340 | If Not Check, if the APIC is integrated or a separate chip Then lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV) | 
| 343 | If Not irqen Then lvtt_value |= APIC_LVT_MASKED | 
| 346 | apic_write(APIC_LVTT, lvtt_value) | 
| 348 | If lvtt_value & APIC_LVT_TIMER_TSCDEADLINE Then | 
| 354 | asm volatile | 
| 356 | Print a one-time message (analogous to WARN_ONCE() et al):(debug-level messages "TSC deadline timer enabled\n") | 
| 357 | Return | 
| 364 | apic_write(APIC_TDCR, (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | APIC_TDR_DIV_16) | 
| 368 | If Not oneshot Then apic_write(APIC_TMICT, clocks / Clock divisor ) | 
| Name | Describe | 
|---|---|
| lapic_timer_set_periodic_oneshot | |
| calibrate_APIC_clock | 
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