Function report

Linux Kernel

v5.5.9

Brick Technologies Co., Ltd

Source Code:arch\x86\kernel\cpu\cyrix.c Create Date:2022-07-28 07:58:55
Last Modify:2020-03-12 14:18:49 Copyright©Brick
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Name:init_cyrix

Proto:static void init_cyrix(struct cpuinfo_x86 *c)

Type:void

Parameter:

TypeParameterName
struct cpuinfo_x86 *c
193  dir1 = 0
194  buf = x86_model_id
195  const char * p = NULL
201  clear_cpu_cap(c, 0 * 32 + 31)
204  If test_cpu_cap(c, 1 * 32 + 24) Then
205  clear_cpu_cap(c, 1 * 32 + 24)
206  set_cpu_cap(c, Cyrix MMX extensions )
209  do_cyrix_devid( & dir0, & dir1)
211  Reset the slow-loop (SLOP) bit on the 686(L) which is set by some old* BIOSes for compatibility with DOS games. This makes the udelay loop* work correctly, and improves performance.* FIXME: our newer udelay uses the tsc. We don't need to frob with SLOP
213  Cx86_dir0_msb is a HACK needed by check_cx686_cpuid/slop in bugs.h in* order to identify the Cyrix CPU model after we're out of setup.c* Actually since bugs.h doesn't even reference this perhaps someone should* fix the documentation ??? = dir0_msn = dir0 >> 4
214  dir0_lsn = dir0 & 0xf
217  x86_model = (dir1 >> 4) + 1
218  x86_stepping = dir1 & 0xf
229  Case dir0_msn == 0
230  p = Cx486_name[dir0_lsn & 7]
231  Break
233  Case dir0_msn == 1
234  p = If dir0_lsn & 8 Then Cx486D_name[dir0_lsn & 5] Else Cx486S_name[dir0_lsn & 3]
236  Break
238  Case dir0_msn == 2
239  Cx86_cb[2] = cyrix_model_mult1[dir0_lsn & 5]
240  p = Cx86_cb + 2
241  Break
243  Case dir0_msn == 3
244  Cx86_cb[1] = ' '
245  Cx86_cb[2] = cyrix_model_mult1[dir0_lsn & 5]
246  If dir1 > 0x21 Then
247  Cx86_cb[0] = 'L'
248  p = Cx86_cb
249  x86_model++
250  Else p = Cx86_cb + 1
253  set_cpu_cap(c, Cyrix ARRs (= MTRRs) )
255  set_cpu_bug(c, Cyrix 6x86 coma )
256  Break
258  Case dir0_msn == 4
259  Case dir0_msn == 11
294  KB - valid for CPUS which support this call: = 16
297  If Maximum supported CPUID level, -1=no CPUID: == 2 Then
299  setCx86(CX86_CCR7, NSC/Cyrix CPU indexed register access. Must be inlined instead of* macros to ensure correct access ordering* Access order is always 0x22 (=offset), 0x23 (=value) | 1)
307  If 0x30 <= dir1 && dir1 <= 0x6f || 0x80 <= dir1 && dir1 <= 0x8f Then Configure later MediaGX and/or Geode processor.
310  Return
311  Else
312  Cx86_cb[2] = If dir0_lsn & 1 Then '3' Else '4'
313  p = Cx86_cb + 2
314  x86_model = If dir1 & 0x20 Then 1 Else 2
316  Break
318  Case dir0_msn == 5
319  If dir1 > 7 Then
320  dir0_msn++
322  setCx86(CX86_CCR7, NSC/Cyrix CPU indexed register access. Must be inlined instead of* macros to ensure correct access ordering* Access order is always 0x22 (=offset), 0x23 (=value) | 1)
323  Else
325  set_cpu_bug(c, Cyrix 6x86 coma )
327  tmp = If Not (dir0_lsn & 7) || dir0_lsn & 1 Then 2 Else 0
328  Cx86_cb[tmp] = cyrix_model_mult2[dir0_lsn & 7]
329  p = Cx86_cb + tmp
330  If (dir1 & 0x0f) > 4 || (dir1 & 0xf0) == 0x20 Then x86_model++
333  set_cpu_cap(c, Cyrix ARRs (= MTRRs) )
334  Break
336  Case dir0_msn == 0xf
338  Case dir0_lsn == 0xd
339  dir0_msn = 0
340  p = Cx486_name[!!boot_cpu_has(Onboard FPU )]
341  Break
343  Case dir0_lsn == 0xe
344  dir0_msn = 0
345  p = Cx486S_name[0]
346  Break
348  Break
350  Default
351  dir0_msn = 7
352  Break
354  strcpy(buf, Cx86_model[dir0_msn & 7])
355  If p Then strcat(buf, p)
357  Return
Caller
NameDescribe
init_nscHandle National Semiconductor branded processors